1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a method of manufacturing the same, and more particularly to a floating gate memory cell and a method of manufacturing the same.
2. Description of the Related Art
In the nonvolatile semiconductor memory, such as an EPROM (erasable programmable read only memory) of the ultraviolet rays erasing type and an EEPROM (electrically erasable read only memory), floating gate type MOS transistors are used for the memory cells. The memory cells of the EPROM using a p-type silicon substrate are manufactured through a manufacturing process as shown in FIGS. 1A through 1D. As shown in FIG. 1A, a field insulating film (not shown) is first formed on the surface of p-type silicon substrate 51 by a known process, for the element isolation defining element formed areas. A gate insulating film 52 is then formed on the surface of the substrate 51. A first polycrystalline silicon layer 53 is deposited over the enter entire surface of the insulating film. Thereafter, a silicon oxide film 54 is formed on the polycrystalline silicon layer 53. Subsequently, a second polycrystalline silicon layer 55 is deposited over the entire surface of the silicon oxide film. A resist pattern 71 for transistor formation is formed on the second polycrystalline silicon layer.
As shown in FIG. 1B, the second polycrystalline silicon layer 55, silicon oxide film 54, first polycrystalline silicon layer 53, and gate insulating film 52 are successively and selectively etched to form cell transistor regions, a control gate electrode 55, and a floating gate 53, by using the resist pattern 71 as a mask. Thereafter, using the control gate electrode 55 as a mask, an n-type impurity is ion implanted into the substrate 51. Subsequently, a silicon oxide film 56 is formed on the surface of the transistor region including the control electrode 55 and the floating gate electrode 53, by thermal oxidizing process. In this case, an n.sup.+ diffusion layer to be a source region 57 and a drain region 58 is also formed simultaneously.
Then, a CVD (chemical vapor growth deposition) oxide film as an interlayer insulating film 59 is deposited over the entire surface of the structure by chemical vapor growth deposition (CVD) process. The entire surface of the structure is coated with a resist 60. The resist 60 is patterned. Using the formed resist pattern as a mask, the CVD oxide film 59 is etched to open a contact hole 61 above the drain region 58. As shown in FIG. 1C, a reactive ion etching process (RIE) is applied to the structure, to remove the insulating oxide film 56 on the bottom surface of the contact hole. Then, the resist 60 is removed. Aluminum is deposited over the entire major surface of the structure, to form an aluminum film. Then, its entire surface is coated with resist. The resist is patterned while referring to the contact hole. By using the resultant resist pattern as a mask, the aluminum film is selectively etched away to form an aluminum interconnection pattern 62.
After, an interlayer insulating film and pads are formed on the aluminum interconnection pattern by the ordinary IC manufacturing process, to complete an EPROM integrated circuit.
However, the EPROM cells thus formed have the following disadvantages.
In the above manufacturing method, a satisfactory amount of the tolerance for the mask alignment is required for opening the contact hole 61. Otherwise, poor insulation may be set up between the gate electrodes 53 and 55, and the aluminum interconnection pattern 62. Further, the microfabrication and high density of integration of electronic elements are essential factors for cost reduction of the resultant integrated circuits. In this respect, the tolerance for the mask alignment is important. The above manufacturing method requires a fixed amount of tolerance that is determined by the accuracy of an exposing system used.
Further, according to the above method, an oxide film is naturally formed on the bottom surface of the contact hole during a period from the opening of the contact hole 61 until the formation of the aluminum interconnection pattern 62. The naturally grown oxide film degrades an electrical connection between the aluminum interconnection layer and the drain region, resulting in an increase of the contact resistance at the contact portion.
In the EPROM, when the charge stored in the floating gate electrode varies by .DELTA.Q, a change of the threshold voltage of the memory cell occurs; the change is given by .DELTA.Vth=.DELTA.Q/C, where C is a capacitance between the control electrode and the floating gate electrode. The change provides a discrimination of "0" from "1" and vice versa.
If movable ions such as Na.sup.+ ions enter the silicon oxide film in the periphery of the floating gate electrode, the amount of the stored charge in the floating gate electrode apparently decreases. Accordingly, the threshold voltage varies, degrading the reliability of the memory cell. It was confirmed that with progression of the microfabrication of the cells, a charge change .DELTA.Q one by several the conventional charge change produces 0.5 or more of the threshold variation. Such movable ions such as Na.sup.+ ion attach to the side wall and the bottom surface of the contact hole, and most of the movable ions is contained in the interconnection material (aluminum) 63 deposited thereon. The movable ions enter the cell from an interface between the aluminum interconnection portion 62 in the contact hole 61 and the CVD insulating film 59 and through the silicon oxide film portion 56 formed between the CVD insulating film 9 and the n.sup.+ diffusion layers 57 and 58 in the surface region of the silicon substrate. The entered movable ions shift the threshold value Vth, possibly causing soft error, and hence degradation of the cell reliability. The above fact was confirmed by us.
If a further microfabrication of the memory allows the scalling of 1/K element size and K times impurity concentration, the power voltage cannot be reduced to 1/K. In this case, an intensity of a peak electric field in the drain depletion layer becomes excessive, and the hot carriers generated increases. In the n-channel EPROM cell, to write data, by applying a high voltage to the control gate electrode, a high voltage is applied to the drain, causing hot carriers, and those hot carriers are injected into the floating gate electrode. To read out data, by applying an ordinary power voltage to the control gate electrode, the voltage applied to the drain is controlled to such a voltage preventing generation of hot electrons. A difference between the threshold voltages provides a discrimination of "0" from "1" of the read data. With microfabrication progression, the hot electrons tend to occur. Under this condition, unexpected electrons are possibly injected into the floating gate electrode, so that the soft error tends to occur and the reliability of the cells is degraded.